// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX : 
// IP Name      : 
//                
// File name    :
// Module name  : 
// Full name    :
//
// Author       :  Hbing 
// Email        :  2629029232@qq.com
// Data         :  2020/8/24
// Version      :  V 1.0 
// 
//Abstract      :
// Called by    :  Father Module
// 
// Modification history
// ------------------------------------------------------------------------------------------------------
// 
//  
// *********************************************************************
// `include "top_define.v"
// *******************
// *******************
// DESCRIPTION
// *******************
// 将宽度16深度33的ram改为寄存器，加快查找速率
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 


module queue_infor_ram_w16_d33_reg(
input  wire            clk       , // input clka
input  wire            wea       , // input  [0 : 0] wea
input  wire [5 : 0]    addra     , // input  [5 : 0] addra
input  wire [15: 0]    dina      , // input  [15: 0] dina
output reg  [15: 0]    douta     , // output [15: 0] douta
input  wire            rst_n     , // input rst_n
input  wire            web       , // input  [0 : 0] web
input  wire [5 : 0]    addrb     , // input  [5 : 0] addrb
input  wire [15: 0]    dinb      , // input  [15 : 0] dinb
output reg  [15: 0]    doutb     
 );

reg [15:0]      douta_reg               ;
reg [15:0]      doutb_reg               ;
reg [15:0]      queue_infor_reg [0:32]  ;



//输出
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        // reset
        douta <= 16'b0;
    end
    else if (wea) begin
        douta <= douta_reg;
    end
    else begin
        case (addra)
        6'd0  : begin
            douta <= queue_infor_reg[0 ];
        end 
        6'd1  : begin 
            douta <= queue_infor_reg[1 ];
        end 
        6'd2  : begin 
            douta <= queue_infor_reg[2 ];
        end 
        6'd3  : begin 
            douta <= queue_infor_reg[3 ];
        end 
        6'd4  : begin 
            douta <= queue_infor_reg[4 ];
        end 
        6'd5  : begin 
            douta <= queue_infor_reg[5 ];
        end 
        6'd6  : begin 
            douta <= queue_infor_reg[6 ];
        end 
        6'd7  : begin 
            douta <= queue_infor_reg[7 ];
        end 
        6'd8  : begin 
            douta <= queue_infor_reg[8 ];
        end 
        6'd9  : begin 
            douta <= queue_infor_reg[9 ];
        end 
        6'd10 : begin 
            douta <= queue_infor_reg[10];
        end 
        6'd11 : begin
            douta <= queue_infor_reg[11];
        end
        6'd12 : begin
            douta <= queue_infor_reg[12];
        end
        6'd13 : begin
            douta <= queue_infor_reg[13];
        end
        6'd14 : begin
            douta <= queue_infor_reg[14];
        end
        6'd15 : begin
            douta <= queue_infor_reg[15];
        end
        6'd16 : begin
            douta <= queue_infor_reg[16];
        end
        6'd17 : begin
            douta <= queue_infor_reg[17];
        end
        6'd18 : begin
            douta <= queue_infor_reg[18];
        end
        6'd19 : begin
            douta <= queue_infor_reg[19];
        end
        6'd20 : begin
            douta <= queue_infor_reg[20];
        end
        6'd21 : begin
            douta <= queue_infor_reg[21];
        end
        6'd22 : begin
            douta <= queue_infor_reg[22];
        end
        6'd23 : begin
            douta <= queue_infor_reg[23];
        end
        6'd24 : begin
            douta <= queue_infor_reg[24];
        end
        6'd25 : begin
            douta <= queue_infor_reg[25];
        end
        6'd26 : begin
            douta <= queue_infor_reg[26];
        end
        6'd27 : begin
            douta <= queue_infor_reg[27];
        end
        6'd28 : begin
            douta <= queue_infor_reg[28];
        end
        6'd29 : begin
            douta <= queue_infor_reg[29];
        end
        6'd30 : begin
            douta <= queue_infor_reg[30];
        end
        6'd31 : begin
            douta <= queue_infor_reg[31];
        end
        6'd32 : begin
            douta <= queue_infor_reg[32];
        end
        default: begin
            douta <= 16'd0;
        end
        endcase
    end
end
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        // reset
        douta_reg <= 16'b0;
    end
    else begin
        douta_reg <= douta;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        // reset
        doutb <= 16'b0;
    end
    else if (web) begin
        doutb <= doutb_reg;
    end
    else begin
        case (addra)
        6'd0  : begin
            doutb <= queue_infor_reg[0 ];
        end 
        6'd1  : begin 
            doutb <= queue_infor_reg[1 ];
        end 
        6'd2  : begin 
            doutb <= queue_infor_reg[2 ];
        end 
        6'd3  : begin 
            doutb <= queue_infor_reg[3 ];
        end 
        6'd4  : begin 
            doutb <= queue_infor_reg[4 ];
        end 
        6'd5  : begin 
            doutb <= queue_infor_reg[5 ];
        end 
        6'd6  : begin 
            doutb <= queue_infor_reg[6 ];
        end 
        6'd7  : begin 
            doutb <= queue_infor_reg[7 ];
        end 
        6'd8  : begin 
            doutb <= queue_infor_reg[8 ];
        end 
        6'd9  : begin 
            doutb <= queue_infor_reg[9 ];
        end 
        6'd10 : begin 
            doutb <= queue_infor_reg[10];
        end 
        6'd11 : begin
            doutb <= queue_infor_reg[11];
        end
        6'd12 : begin
            doutb <= queue_infor_reg[12];
        end
        6'd13 : begin
            doutb <= queue_infor_reg[13];
        end
        6'd14 : begin
            doutb <= queue_infor_reg[14];
        end
        6'd15 : begin
            doutb <= queue_infor_reg[15];
        end
        6'd16 : begin
            doutb <= queue_infor_reg[16];
        end
        6'd17 : begin
            doutb <= queue_infor_reg[17];
        end
        6'd18 : begin
            doutb <= queue_infor_reg[18];
        end
        6'd19 : begin
            doutb <= queue_infor_reg[19];
        end
        6'd20 : begin
            doutb <= queue_infor_reg[20];
        end
        6'd21 : begin
            doutb <= queue_infor_reg[21];
        end
        6'd22 : begin
            doutb <= queue_infor_reg[22];
        end
        6'd23 : begin
            doutb <= queue_infor_reg[23];
        end
        6'd24 : begin
            doutb <= queue_infor_reg[24];
        end
        6'd25 : begin
            doutb <= queue_infor_reg[25];
        end
        6'd26 : begin
            doutb <= queue_infor_reg[26];
        end
        6'd27 : begin
            doutb <= queue_infor_reg[27];
        end
        6'd28 : begin
            doutb <= queue_infor_reg[28];
        end
        6'd29 : begin
            doutb <= queue_infor_reg[29];
        end
        6'd30 : begin
            doutb <= queue_infor_reg[30];
        end
        6'd31 : begin
            doutb <= queue_infor_reg[31];
        end
        6'd32 : begin
            doutb <= queue_infor_reg[32];
        end
        default: begin
            doutb <= 16'd0;
        end
        endcase
    end
end
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        // reset
        doutb_reg <= 16'b0;
    end
    else begin
        doutb_reg <= doutb;
    end
end

//reg 信息维护
genvar i;
generate
    for (i = 0; i < 33; i = i + 1) begin: gen_queue_infor
        always @(posedge clk or negedge rst_n) begin
            if (~rst_n) begin
                queue_infor_reg[i] <= 32'b0;
            end
            else if ((addra == i) && wea) begin
                queue_infor_reg[i] <= dina;
            end
            else if((addrb == i) && web) begin
                queue_infor_reg[i] <= dinb;
            end
            else begin
                queue_infor_reg[i] <= queue_infor_reg[i];
            end
        end
    end 
endgenerate

endmodule
